Spin-Torque Transfer Random Access Memory (STTRAM) is a useful memory technology for embedded cache due to high-density, low standby power, and high speed [1]. STTRAM provides high density due to a 1T-1R structure and can eliminate bitcell leakage due to the non-volatile nature of the storage element, which is a magnetic tunnel junction (MTJ). Referring to FIG. 1(a), the MTJ can contain a free layer and a pinned magnetic layer. The resistance of the MTJ stack is high if the free layer magnetic orientation is anti-parallel compared to the fixed layer, and the resistance of the MTJ stack is low if the free layer magnetic orientation is parallel compared to the fixed layer. The configuration of the MTJ can be changed from parallel to antiparallel, or vice versa, by injecting current from the source-line to the bitline, or vice versa. The spin-torque transfer phenomena for reversal of magnetization in a free layer reduce the write power compared to conventional Magnetic Random Access Memory (MRAM). The memory array can contain a circuit to sense the orientation of the free magnetic layer compared to fixed layer.
Challenges involved in STTRAM include high write current, long write time, and poor sense margin (SM). Sense margin of STTRAM depends on the tunnel magnetic ratio (TMR), which is defined as 100*(RHRL/RL) where RL and RH are low and high resistance, respectively, of the MTJ. Due to a poor TMR, the voltage/current differential between RH and RL can decrease, which can degrade the SM. In addition, SM is asymmetric in nature, meaning that SM0 and SM1 are not identical [6]. FIG. 2 is a chart showing the taxonomy of various sensing techniques. Referring to FIG. 2, STTRAM sensing can be broadly categorized into destructive and non-destructive sensing. Several non-destructive sensing techniques exist, including a nondestructive voltage sensing and sizing methodology to improve the SM of MRAM arrays, as well as a source degeneration scheme to reduce large SM variation [2, 3, 4, 5, 6, 8, 11, 12, 13]. Even though the read latency and power can be reduced using certain techniques, for example by eliminating two write steps, the SM is much smaller than with destructive self-reference schemes and conventional nondestructive voltage sensing.
A destructive (self-reference) sensing technique exits that can eliminate bit-to-bit process variation in MTJ resistance [7]. Sensing is performed by first storing the voltage of the MTJ by passing a current (I1), and then after a time interval storing a reference voltage of the same MTJ after passing another current (I2). The variation in MTJ resistance can be eliminated by this self-reference sensing scheme. Although this mechanism can provide better SM and decrease the need for reference voltage, it incurs high power consumption and long read latency due to two write steps.